The present invention relates to a DMA transfer control device for transferring data between devices.
Conventionally, a DMA transfer method for performing a direct data transfer between transfer devices without the intervention of a CPU has been widely known, and used to allow, e.g., a data transfer from one memory to another to be performed directly between the memories.
In a DMA transfer, a transfer operation is executed in such a manner that information necessary for the transfer, such as a data transfer source initiation address, a data transfer destination initiation address, and a data transfer size, is set to a register or the like in a DMA transfer control device, and then a CPU or the like controls the initiation of the transfer. During the transfer, the CPU need not control the transfer. Accordingly, the data transfer can be performed at a higher speed than in the case where the transfer is performed via the CPU, and a load on the CPU can be reduced. When the transfer of data equivalent to the transfer size which is set to the register or the like is completed, a DMA transfer complete interrupt is asserted in accordance with the setting of the DMA transfer control device. On sensing the DMA transfer complete interrupt, the CPU reads information from the register or the like in the DMA transfer control device, and monitors the result of the DMA transfer and the status thereof.
A DMA transfer is mostly used in the case where a plurality of transfer requests are sent, and the same content is transferred or a plurality of DMA transfers are performed from the subsequent addresses. For example, when data is transferred from a peripheral device to a memory, a transfer request is issued after checking the amount of data stored in the FIFO butter of the peripheral device, and a DMA transfer is performed in response to the issued transfer request. This process is performed by the determined total number of transfers.
In the structure described above, when an interrupt is generated in the CPU every time one DMA transfer is completed, transfer informations need to be set every time the interrupt is generated so that transfer efficiency deteriorates. In addition, when data is accumulated in the FIFO buffer before a DMA transfer is performed by re-setting transfer informations to the DMA control device, the FIFO buffer incurs an overflow so that a problem occurs in system.
To counteract such a problem, there has been proposed a conventional DMA transfer control device described in Japanese Laid-Open Patent Publication No. 2002-73527. In the DMA transfer control device, a DMA transfer is repeatedly performed by the number of times set to a number-of-transfers register. Specifically, as shown in FIG. 11, there are provided a CYC register 60 for setting the number of data transfers to be performed in response to one DMA transfer request, a CYC counter 61 for counting the number of data transfers that have been performed, and a TRN counter 52 for updating a value held therein every time the data transfers, the number of which equals the number held in the CYN resister 60, are performed. The data transfers are performed by repeating the operation describe above till the TRN counter 62 reaches a predetermined number.
In the conventional transfer control device, the total amount of data transferred by DMA is given by multiplying the set value (A) in the CYC register 60 by the set value (B) in the TRN counter 62. However, the total amount of data to be transferred by DMA is not necessarily an integral multiple of the set value (A). Accordingly, the total amount of data to be transferred by DMA does not match the product (A)×(B) of the set values (A) and (B), and a fraction may occur occasionally. To implement a transfer at this time, there can be considered the following methods.
1. After data corresponding to the product (A)×(B) is completely transferred, an interrupt is issued to the CPU such that settings are made again for the transfer of data in an amount corresponding to the fraction, and the transfer is executed.
2. The set values are changed so as to reduce the amount of data to be transferred in accordance with the fraction, and provide (A′)×(B′).
3. In addition to the DMA transfer, a dummy transfer is also performed to adjust the total amount of data to be transferred by DMA to the product value (A)×(B).
However, each of the methods mentioned above also has disadvantages. For example, in the method 1 mentioned above, it is necessary to make settings again for the transfer of data corresponding to the fraction after the data other than that corresponding to the fraction is transferred. This involves the additional trouble of setting software. On the other hand, in the method 2 mentioned above, the amount of data which can be transferred by issuing one DMA transfer request is reduced so that the speed of the transfer is also reduced. In addition, there is also a case where, because the transfer speed is less than a required value, data overflows and cannot be retrieved. Further, in the method 3, required data is overwritten by another data as a result of a dummy transfer.
In the prior art technology described above, every time a DMA transfer request is issued, the same setting register is used for a DMA transfer performed in response to the DMA transfer request, and a transfer source initiation address, a transfer destination initiation address, and the like are also fixed or continued from those in the previous DMA transfer. Accordingly, in the case where the amount of data to be transferred is intended to be temporarily changed, or a transfer address is intended to be changed, the settings cannot be flexibly changed.